Topic hub

PLC Programming

Ladder logic, structured text and the instructions you actually use on a job: contacts and coils, timers, counters, one-shots, latches, sequencers and the addressing rules underneath them.

This is the core of the site. Start with how the scan cycle evaluates a rung, then work through the instruction families in the order you will meet them on a real machine: contacts and coils, seal-in circuits, TON and TOF timers, counters, edge detection, and finally step sequencers. Every article here pairs the theory with a rung you can open and run in the browser.

37 articles in this hub

Split infographic comparing a hardwired relay control panel on the left with a PLC rack and ladder logic display on the right, showing relay coils and contacts versus digital I/O modules
relay logicplc programmingladder logic

Relay Logic vs PLC Logic: Key Differences Explained

Relay logic vs PLC logic: a practical comparison covering speed, flexibility, cost, troubleshooting and when hardwired relays still beat a PLC on the plant floor.

Aug 9, 2026 路 9 min read

Flat vector infographic comparing a relay output PLC module connected to an AC load and a transistor output module connected to a DC load, showing their internal switching elements side by side
plc outputsrelay outputtransistor output

Relay vs Transistor PLC Outputs: Full Comparison

Relay output vs transistor output on a PLC: pick the wrong one and you'll burn contacts or miss high-speed counts. Here's exactly how they differ and when each wins.

Aug 8, 2026 路 8 min read

Flat vector diagram of a Studio 5000 Logix Designer ladder editor open on a laptop connected to a ControlLogix rack and EtherNet/IP network
studio 5000logix designerallen-bradley

Studio 5000 Interview Questions: Real Answers

Preparing for a Studio 5000 or Logix Designer interview? These 15 real questions cover tags, tasks, AOIs, EtherNet/IP, and safety, with field-tested answers.

Aug 7, 2026 路 12 min read

Flat vector diagram showing a PLC programmer interview checklist alongside a PLC rack and ladder logic rung symbol
plc programmer interviewplc interview questionsplc programming basics

PLC Programmer Interview Questions: Real Answers

Preparing for a PLC programmer interview? These 30 real questions cover scan cycle, memory, I/O, timers, counters, comms and more, with answers that go beyond textbook definitions.

Aug 6, 2026 路 15 min read

Flat vector diagram of an Allen-Bradley ControlLogix rack connected to an HMI via EtherNet/IP with floating ladder logic rungs and Studio 5000 tag labels
allen-bradleystudio 5000controllogix

Allen-Bradley PLC Interview Questions: Real Answers

Preparing for an Allen-Bradley PLC role? These 25 interview questions cover Studio 5000, ControlLogix, tags, EtherNet/IP and ladder logic with concrete, field-tested answers.

Aug 6, 2026 路 16 min read

Flat vector diagram comparing relay, transistor and triac PLC output wiring with labeled terminal blocks and load connections
plc output wiringrelay outputtransistor output

PLC Output Wiring: Relay, Transistor and Triac

Relay, transistor and triac PLC outputs wire differently and fail differently. Here is exactly how to connect each type and avoid the mistakes that kill modules.

Aug 4, 2026 路 10 min read

Flat vector diagram showing four PLC counter reset methods connecting to a CTU counter function block with teal accent arrows
plc countersladder logicstudio 5000

PLC Counter Reset: 4 Methods and When to Use Each

Resetting a PLC counter sounds simple until it bites you mid-batch. This guide covers every reset method, when each one is right, and the gotchas that cause missed counts.

Aug 3, 2026 路 8 min read

Flat vector diagram of a PLC counter instruction showing the preset and accumulator fields with a done bit activating when accumulator reaches preset value
plc countersladder logiccounter instructions

PLC Counter Preset vs Accumulator: What Each Does

The preset and accumulator in a PLC counter do very different jobs. This guide explains each one, how they interact, and the real-world gotchas you need to know.

Aug 3, 2026 路 8 min read

Flat vector diagram comparing a CTU count-up and CTD count-down PLC counter instruction side by side with accumulated value bars and ladder rung connections
plc countersctu ctdladder logic

CTU vs CTD: PLC Counter Instructions Compared

CTU counts up from zero; CTD counts down from a preset. Learn when to use each, how they differ across platforms, and how to wire both into working ladder logic.

Aug 2, 2026 路 9 min read

Flat vector diagram of three cascading PLC TON timers in ladder logic where each timer done bit triggers the next step in a timed sequence
plc timersladder logicton timer

Cascading PLC Timers: Chain TON Logic Right

Learn how to cascade TON timers in PLC ladder logic to build reliable multi-step timed sequences. Real examples, common mistakes, and field-tested patterns.

Aug 2, 2026 路 7 min read

Side-by-side timing diagram comparing a retentive PLC timer that holds its accumulated value versus a non-retentive timer that resets to zero when the enable signal drops
plc timersretentive timerladder logic

Retentive vs Non-Retentive PLC Timers: Key Differences

Retentive and non-retentive PLC timers behave completely differently when the enable bit drops. Learn which to use, how each resets, and see real ladder examples across platforms.

Aug 2, 2026 路 8 min read

Flat vector diagram of three PLC timer ladder rungs labeled TON, TOF and TP each with a timing waveform showing input and output signal behavior
plc timersladder logicton tof tp

PLC Timer Ladder Logic: 5 Practical Examples

Five practical PLC timer ladder logic examples covering TON, TOF and TP instructions, with timing diagrams, gotchas and field-tested advice for Rockwell and generic platforms.

Aug 1, 2026 路 8 min read

Flat vector timing diagram comparing a TON timer that resets on false rung with a retentive TONR timer that holds its accumulated value across multiple enable pulses
retentive timerplc timersladder logic

Retentive Timer in PLC Ladder Logic Explained

A retentive timer keeps its accumulated value when power is lost or the rung goes false. Learn how TONR works, when to use it, and see real ladder examples.

Aug 1, 2026 路 9 min read

Flat vector ladder logic diagram showing a set-reset flip-flop with OTL and OTU latch coils driving a shared output tag on a PLC rack
ladder logicset reset flip flopplc programming

Set-Reset Flip-Flop in Ladder Logic: Full Guide

Learn how the set-reset flip-flop works in PLC ladder logic, how it differs from a seal-in rung, and when each pattern belongs in your program.

Aug 1, 2026 路 8 min read

Flat vector diagram showing a PLC input signal falling edge triggering a single OSF one-shot output pulse in ladder logic
one-shotedge detectionladder logic

Falling-Edge One-Shot in Ladder Logic: OSF Explained

The OSF instruction fires a single scan pulse on a signal's falling edge. Learn exactly how it differs from OSR, where it saves you from logic bugs, and see a real worked example.

Jul 31, 2026 路 8 min read

PLC ladder logic rung showing an OSR one-shot rising instruction converting a sustained input signal into a single-scan output pulse
ladder logicone-shotedge detection

One-Shot Rising Edge in Ladder Logic: OSR Explained

Learn how the OSR (one-shot rising) instruction works in PLC ladder logic, when to use it, and how to avoid the single-scan pitfall that catches every newcomer.

Jul 31, 2026 路 8 min read

Flat vector infographic showing four ladder logic interlock rung patterns for PLC programming, including permissive, mutual exclusion, run confirm and safety guard circuits
ladder logicinterlocksplc programming

Ladder Logic Interlocks: How They Work and Why

Ladder logic interlocks stop dangerous or invalid machine states before they happen. Learn the four core interlock patterns, see real rung examples, and avoid the wiring gotchas that bite engineers on commissioning day.

Jul 31, 2026 路 8 min read

Flat vector ladder logic diagram showing OTL latch coil and OTU unlatch coil rungs with a shared retentive bit and memory icon
ladder logiclatching coilplc programming

OTL and OTU Latch Coils in Ladder Logic Explained

OTL and OTU latch coils hold state through a power cycle. Learn how they work in ladder logic, how they differ from seal-in rungs, and when each belongs in your program.

Jul 30, 2026 路 8 min read

Flat vector diagram of a PLC rack showing input module connected to field sensors and output module connected to actuators with signal path arrows through optocouplers
plc i/o modulesplc inputsplc outputs

How PLC Input and Output Modules Work

PLC input and output modules are more than just terminal strips. Learn exactly how signals get conditioned, isolated, and mapped into CPU memory on every scan.

Jul 30, 2026 路 9 min read

Flat vector diagram comparing PLC direct addressing, indirect addressing with an array index pointer, and symbolic tag addressing across three memory layout panels
plc addressingladder logicplc programming basics

PLC Addressing Modes: Direct, Indirect and Symbolic

Direct, indirect and symbolic addressing each work differently inside a PLC. This guide breaks down how each mode works, when to use it, and the gotchas that catch engineers off guard.

Jul 30, 2026 路 9 min read

Flat vector infographic of the PLC scan cycle showing four phases arranged in a circle: input scan, program execution, output scan, and housekeeping with connecting arrows
plc scan cycleplc basicsladder logic

How the PLC Scan Cycle Works: Step by Step

The PLC scan cycle is the heartbeat of every control system. Learn exactly what happens during input scan, program execution, and output scan, with real numbers and field gotchas.

Jul 29, 2026 路 10 min read

Flat vector diagram of a PLC rack with internal bit memory cells highlighted in teal and grey showing how internal flags connect input and output logic rungs
internal bitsplc flagsladder logic

PLC Internal Bits: Flags, Coils and How to Use Them

Internal bits, flags and internal coils let your PLC logic communicate with itself across rungs. Learn what they are, how to use them correctly, and the gotchas that trap beginners.

Jul 29, 2026 路 9 min read

Flat vector diagram of a PLC controller rack showing CPU, I/O modules, power supply, and connections to sensors and actuators representing a complete PLC system
plc basicsplc programmingwhat is a plc

What Is a PLC Controller and How Does It Work?

Learn what a PLC controller is, how it executes logic in a repeating scan cycle, and how inputs, outputs, and memory work together to control real machines.

Jul 29, 2026 路 8 min read

Flat vector diagram showing a laptop running a ladder logic simulation with ghost PLC rack and sensor icons connected by dashed lines, representing offline PLC simulation
ladder logicplc simulationcommissioning

How to Simulate Ladder Logic Without a PLC

Learn how to simulate ladder logic in Studio 5000, TIA Portal and CODESYS so you can catch logic errors before commissioning, with real examples and gotchas.

Jul 20, 2026 路 8 min read

Flat vector diagram comparing normally open and normally closed contact symbols in PLC ladder logic rungs
ladder logicplc contactsnormally open vs normally closed

NO vs NC Contacts in PLC Ladder Logic: Full Breakdown

Confused about normally open vs normally closed contacts in PLC ladder logic? Learn what NO and NC mean in hardware vs software, with real wiring examples.

Jul 20, 2026 路 8 min read

Flat vector diagram comparing PLC, PAC, and DCS controller architectures side by side with I/O modules and network connections illustrated
plc vs pac vs dcscontrol system selectiondcs vs plc

PLC vs PAC vs DCS: Which Controller Do You Need?

PLC, PAC, and DCS all control industrial processes, but they are built around different assumptions. Here is how to tell them apart and pick the right one.

Jul 19, 2026 路 8 min read

Flat vector diagram comparing a PLC rack control system on the left with a distributed DCS cabinet architecture on the right, connected to process plant icons
plc vs dcsdcscontrol systems

PLC vs DCS: Key Differences and How to Choose

PLC vs DCS is one of the most debated choices in industrial automation. This guide cuts through the marketing and gives you a practical, field-tested comparison to help you pick the right platform.

Jul 19, 2026 路 9 min read

Flat vector diagram comparing XIC and XIO ladder logic contact symbols with bit-state labels showing how each instruction evaluates its tag
ladder logicallen-bradleystudio 5000

XIC vs XIO: Ladder Logic Contacts Explained

XIC and XIO are the two most fundamental contacts in Allen-Bradley ladder logic. Learn exactly how each evaluates its bit, where to use them, and the mistakes that catch beginners out.

Jul 19, 2026 路 9 min read

Flat vector infographic comparing TON on-delay, TOF off-delay and TP pulse PLC timer waveforms side by side with labeled input and output signal bars
plc timersladder logiciec 61131-3

TON vs TOF vs TP: PLC Timer Comparison

TON, TOF and TP are the three IEC 61131-3 standard timer types. Learn exactly how each one behaves, where each one fails you, and which to pick for your application.

Jul 19, 2026 路 8 min read

Flat vector diagram of S7-1200 TON TOF and TONR IEC timer function blocks connected to a PLC CPU icon
siemens s7-1200tia portalplc timers

S7-1200 Timers in TIA Portal: TON, TOF and TONR

Learn how TON, TOF and TONR timers work on the S7-1200 in TIA Portal, including IEC timer data types, instance DBs, preset syntax and real wiring gotchas.

Jul 18, 2026 路 9 min read

Flat vector diagram of a PLC rack with a colour-coded memory map showing BOOL, INT, DINT and REAL data type cells
plc data typesplc interview questionsplc programming

PLC Data Types: Interview Questions Answered

Preparing for a PLC interview? These 15 questions on data types, addressing and memory layout cover exactly what hiring engineers ask, with field-tested answers.

Jul 17, 2026 路 9 min read

Diagram of PLC module types in a rack including discrete I/O, analog I/O, communications and specialty modules
plc modulesplc i/oplc hardware

Types of PLC Modules: I/O, Comms and More

From discrete I/O cards to specialty motion modules, learn what every type of PLC module does, how they differ, and when to use each one.

Jul 17, 2026 路 11 min read

Flat vector diagram of a ladder logic rung showing XIC and XIO contacts connected to an OTE output coil with a TON timer block, representing ladder logic interview questions
ladder logicplc interviewplc programming basics

Ladder Logic Interview Questions: Real Answers

Preparing for a PLC role? These ladder logic interview questions cover contacts, coils, timers, counters, latching, scan cycle, and common gotchas interviewers love to probe.

Jul 16, 2026 路 13 min read

TON TOF TONR PLC timer comparison diagram showing input and output timing waveforms
timersladder logicplc programming

TON, TOF and TONR Timers: What Actually Differs

TON, TOF and TONR timers behave very differently under power loss and input cycling. Here's exactly how each one works, with real ladder examples and common gotchas.

Jul 7, 2026 路 7 min read

CTU CTD and CTUD PLC counter instructions diagram showing preset and accumulated count values
countersladder logicplc programming

PLC Counter Instructions: CTU, CTD and CTUD Explained

CTU, CTD and CTUD counters explained with real preset values, accumulated counts, reset behaviour, and vendor-specific differences you need to know.

Jul 7, 2026 路 9 min read

Five types of PLC programming languages shown as flat vector icons representing IEC 61131-3 standard
plc programming languagesiec 61131-3ladder logic

5 Types of PLC Programming Languages Explained

IEC 61131-3 defines five PLC programming languages. Here is a plain-English breakdown of each, with real examples and honest advice on which to pick.

Jul 4, 2026 路 7 min read

PLC memory addressing map showing input, output, bit memory and data block segments
plc memoryaddressingdata types

PLC Memory and Addressing Explained

PLC memory addressing controls every tag, bit, byte and word your program touches. Here is how it really works across Siemens, Rockwell and CODESYS platforms.

Jul 4, 2026 路 8 min read